1. Field of the Invention
The present invention relates to a formation method of a contact/through hole and more particularly, to a formation method of a contact hole or a through hole for electrically interconnecting an upper electrical conductor with a lower electrical conductor through a dielectric layer intervening between the upper and lower conductors, which is applicable to fabrication of an Ultra-Large-Scale Integrated circuit (ULSI).
2. Description of the Prior Art
Various patterning processes for electrically-conductive or dielectric layers are performed in a ULSI fabrication sequence.
With a typical patterning process of this sort, a wanted Pattern of geometrical shapes is formed in a resist film using a lithography technique. Then, unnecessary materials are selectively removed by an etching process using the resist film with the pattern as a mask. This mask serves to protest an underlying layer or layers with respect to the mask during this etching process.
In a formation process of a contact or through hole penetrating an interlayer dielectric layer to electrically interconnect an upper electrical conductors with a lower electrical conductor, two known masking techniques may be utilized.
A first one of the masking techniques utilizes a patterned photoresist film as a mask. A second one of the masking techniques utilizes a hard mask layer made of an inorganic material such as polycrystalline silicon (i.e., polysilicon).
When a contact or through hole is formed to penetrate an interlayer dielectric layer using the first masking technique, it is sufficient to pattern the photoresist film by a lithography technique, forming a window or hole pattern penetrating through the photoresist film. The patterned photoresist film thus obtained serves as a mask during a subsequent etching process, in which a penetrating hole serving as the contact or through hole is formed in the interlayer dielectric layer at a corresponding location to the window of the photoresist film.
To maintain the critical dimension control of the pattern on the photoresist film within a specific range, an etchant for this etching process needs to have a sufficient etch selectivity between the photoresist film and the interlayer dielectric layer so that the thickness of the photoresist film is kept approximately unchanged even after completion of this etching process.
Subsequently, the patterned photoresist film is removed by contacting this photoresist film with an oxygen (O.sub.2) plasma that incinerates the photoresist film and/or a solvent in which the photoresist film is soluble.
Further, the contact or through hole formed in the interlayer dielectric layer is filled with an electrically-conductive material, resulting in an electrically-conductive plug that electrically interconnects an upper electrical conductor with a lower electrical conductor.
When a contact or through hole is formed in an interlayer dielectric layer using the second masking technique, first, the photoresist film is patterned by a photolithography technique, forming a window or hole pattern penetrating through the photoresist film. Next, the pattern of the photoresist film thus formed is transferred to an underlying hard mask layer (i.e., a first hard mask layer) by an etching process, forming a hole penetrating the hard mask layer at a location corresponding to the window of the photolithography film. The patterned photoresist film is then removed.
At this stage, if it is determined that the transferred hole onto the first hard mask layer is excessively large, a thin mask layer (i.e., a second hard-mask layer), which is made of the same material as that of the first hard mask layer, is formed on the first hard mask layer to have the same contour as that of the transferred hole. The second hard mask layer thus formed is then removed during a subsequent anisotropic dry etching process.
During this anisotropic dry etching process, although the second hard mask layer is removed from the horizontal surfaces such as the hole bottom of the hard mask layer and the hole top thereof, it is left unchanged from the vertical surfaces such as the hole sidewall of the hard mask layer. As a result, the initial size of the hole of the first hard mask layer is reduced by approximately twice the thickness of the second hard mask layer.
The second mask layer serves as a mask during a subsequent etching process, in which a penetrating hole serving as the contact or through hole is formed in the interlayer dielectric layer at a corresponding location to the hole of the second hard mask layer.
To maintain the critical dimension control of the pattern on the second hard mask layer within a specific range, an etchant for this etching process needs to have a sufficient etch selectivity between the second hard mask layer and the interlayer dielectric layer so that the thickness of the second hard mask layer is kept approximately unchanged even after this etching process.
A most-popular hard mask layer for contact-hole formation is made of polysilicon having a comparatively-high etching resistance during a reactive-ion etching (RIE) process for silicon dioxide (SiO.sub.2). In this case, after an etching process for a contact hole is completed, a polysilicon hard mask layer is left on the surface of a semiconductor wafer. In addition to using polysilicon in the polysilicon hard mask layer, a polysilicon plug layer is commonly used for plugging a contact hole formed in a SiO.sub.2 layer.
To further miniaturize each of the semiconductor devices and elements on the ULSI, for the upper electrical conductor a conductive layer or layers with an electrical resistance lower than the polysilicon hard mask and plug layers must be used. Hence, after depositing the polysilicon layer to form the plug, both the polysilicon hard mask layer and the polysilicon plug layer must be isotropically etched to either reduce their combined thickness or completely remove them from the wafer surface leaving the polysilicon in the contact hole intact. Since both layers are polysilicon, the etching process is simple. The lower-resistance electrically conductive layer is then deposited on top of the plug. As a result, the polysilicon-plugged contact hole is formed to penetrate through the SiO.sub.2 layer in such a way that the underlying SiO.sub.2 layer is exposed in the vicinity of the top end of the polysilicon-plugged contact hole.
A first typical example of the conventional formation methods of a contact hole using a polysilicon hard mask is shown in FIGS. 1A to 1H.
First, as shown in FIG. 1A, an impurity-doped region 202 is formed in a surface area of a silicon (Si) substrate 201. Next, an interlayer dielectric layer 203 of SiO.sub.2 is formed on the substrate 201 to cover the impurity-doped region 202. A hard mask layer 204 of polysilicon is formed on the interlayer dielectric layer 203.
A patterned photoresist film 205 is formed on the hard mask layer 204. This photoresist film 205 has a window or contact-hole pattern 205A formed by a photolithography technique. The state at this stage is shown in FIG. 1A.
The hard mask layer 204 is selectively etched by an RIE process using the patterned photoresist film 205 as a mask, forming a hole pattern 206 penetrating the hard mask layer 204. The photoresist film 205 is then removed. Thus, the contact-hole pattern 205A of the photoresist film 205 is transferred to the hard mask layer 204, as shown in FIG. 1B.
Subsequently, the interlayer dielectric layer 203 is selectively etched by an RIE process using the polysilicon hard mask layer 204 as a mask, forming a contact hole 207 penetrating the dielectric layer 203, as shown in FIG. 1C. The contact hole 207 exposes the underlying impurity-doped region 202.
A polysilicon layer 208 for an electrically-conductive plug is formed on the hard mask layer 204 to bury the contact hole 207 by a Low-Pressure Chemical Vapor Deposition (LPCVD) process. The contact hole 207 is filled with the polysilicon of the layer 208, as shown in FIG. 1D.
The polysilicon plug layer 208 and the polysilicon hard-mask layer 204 are removed by an isotropic RIE process, resulting in a polysilicon plug 209 in the contact hole 207, as shown in FIG. 1E. The contact hole 207 is fully filled with the plug 209.
An electrically-conductive layer 210 is deposited on the SiO.sub.2 interlayer dielectric layer 203 and the polysilicon plug 209, as shown in FIG. 1F. A patterned resist film 211 is formed on this layer 210 by a lithography technique, as shown in FIG. 1G.
Using the patterned resist film 211 as a mask, the electrically-conductive layer 210 is selectively etched by an RIE process, transferring the pattern of the resist film 211 to the electrically-conductive layer 210. Thus, an upper electrical conductor 212 is formed on the interlayer dielectric layer 203 and the plug 209, as shown in FIG. 1H. The upper electrical conductor 212 is contacted with the polysilicon plug 209 and is electrically connected to the impurity-doped region 202 in the substrate 201 through the plug 209.
A second typical example of the conventional formation methods of a contact hole using a polysilicon hard mask is shown in FIGS. 2A to 2H.
First, as shown in FIG. 2A, an impurity-doped region 202 is formed in a surface area of a silicon substrate 201. Next, an interlayer dielectric layer 203 of SiO.sub.2 is formed on the substrate 201 to cover the impurity-doped region 202. A hard mask layer 204 of polysilicon is formed on the interlayer dielectric layer 203.
A patterned photoresist film 205 is formed on the hard mask layer 204. This photoresist film 205 has a window or contact-hole pattern 205A formed by a photolithography technique. The state at this stage is shown in FIG. 2A.
The hard mask layer 204 is selectively etched by an RIE process using the patterned photoresist film 205 as a mask, forming a hole pattern 206 penetrating the hard mask layer 204. The photoresist film 205 is then removed. Thus, the contact-hole pattern 205A of the photoresist film 205 is transferred onto the hard mask layer 204, as shown in FIG. 2B.
The above processes are the same as those in the first conventional method shown in FIGS. 1A to 1H.
Subsequently, unlike the first conventional method, a thin polysilicon layer 227 is deposited on the patterned polysilicon hard-mask layer 204, as shown in FIG. 2C. The thin polysilicon layer 227 is contacted with the interlayer dielectric layer 203 in the hole pattern 206.
The thin polysilicon layer 206 is then etched by an anisotropic RIE process to be selectively left on the side face of the hard mask layer 204 in the hole pattern 206. Thus, a polysilicon sidewall 228 is formed in the hole pattern 206 of the hard mask layer 204, as shown in FIG. 2D. Thus, the size of the hole pattern 206 is reduced by the sidewall 22B by approximately twice the thickness of the sidewall 228.
The interlayer dielectric layer 203 is selectively etched by an RIE process using the polysilicon hard-mask layer 204 and the polysilicon sidewall 228 as a mask, forming a contact hole 229 penetrating the dielectric layer 203, as shown in FIG. 2D. The contact hole 229 exposes the underlying impurity-doped region 202.
A polysilicon layer 208 for a plug is formed on the hard mask layer 204 to bury the contact hole 229 thus formed by a LPCVD process. The contact hole 229 is filled with the polysilicon of the layer 208, as shown in FIG. 2E.
The polysilicon plug layer 208, the polysilicon hard-mask layer 204, and the polysilicon sidewall 228 are removed by an isotropic RIE process, resulting in a polysilicon plug 229 in the contact hole 229, as shown in FIG. 2F. The contact hole 229 is fully filled with the plug 209.
An electrically-conductive layer 210 is deposited on the SiO.sub.2 interlayer dielectric layer 203 and the polysilicon plug 209, as shown in FIG. 2F. A patterned resist film 211 is formed on this layer 210 by a lithography technique, as shown in FIG. 2G.
Using the patterned resist film 211 as a mask, the electrically-conductive layer 210 is selectively etched by an RIE process, transferring the pattern of the resist film 211 onto the electrically-conductive layer 210. Thus, an upper electrical conductor 212 is formed on the interlayer dielectric layer 203 and the plug 209, as shown in FIG. 2H. The upper electrical conductor 212 is contacted with the polysilicon plug 209 and is electrically connected to the impurity-doped region 202 in the substrate 201 through the plug 209.
The above-described first and second conventional methods using the polysilicon hard mask layer are sufficient for the present ULSIs. However, for the future ULSIs that will be further miniaturized, these methods have the following problems.
A first problem is that the conventional hard-mask technique is unable to be applied to the contact or through holes in the future ULSIs. The reason is as follows.
When each semiconductor device or element on the ULSI is further miniaturized to increase the number of the chips per wafer, each contact or through hole penetrating an interlayer dielectric layer will be further miniaturized. Consequently, the ratio of depth to width (i.e., the aspect ratio) of the hole will become larger. On the other hand, the aspect ratio of a corresponding hole pattern of a resist mask will not become large, because the resist mask needs to be thinner with the decreasing size of the semiconductor devices or elements. The thinner resist mask has a lower etching resistance.
To form the deep contact or through hole in the interlayer dielectric layer using the resist mask, an etching period of time is required to be set as longer. However, in this case, the resist mask is entirely etched away before the hole is completely etched in the interlayer dielectric layer because of the reduced etching resistance of the resist mask.
Accordingly, the above-described conventional hard-mask techniques have a limit for the further-miniaturized future ULSIs.
A second problem is that the conventional hard-mask techniques are readily applicable to only the case where the subsequent plugging method of a contact or through hole using a polysilicon plug includes deposition and etching processes of polysilicon. The conventional hard-mask techniques are not applicable to the future ULSIs with a minimum feature size of a quarter (1/4) .mu.m, because an impurity-doped polysilicon plug filled into a hole with a large aspect ratio does not have a sufficient low electric resistance. Therefore, a metal plug needs to be filled into the hole instead of the polysilicon plug.
In this case, however, the polysilicon hard mask is unable to be s electively removed without etching the exposed silicon substrate at the bottom of the contact hole prior to deposition of a metal for the plug. On the other hand, if the polysilicon hard mask is left intact until deposition of the metal layer for the plug, and then removed during etching of the metal to form the upper electrical conductor, the required etching to remove the metal and polysilicon layers will become more complicated.
Further, the deposition temperature of polysilicon produced by a LPCVD process is typically 500 to 700.degree. C. An electrically-conductive layer located under the interlayer dielectric layer has an insufficient heat resistance against the high temperature of 500 to 700.degree. C. For example, an aluminum alloy will melt at a temperature ranging from 500 to 700.degree. C. Therefore, the polysilicon hard mask is unable to be used to form a through hole in the interlayer dielectric layer.
To solve the above first and second problems, silicon nitride (Si.sub.3 N.sub.4) may be used as the hard mask layer instead of polysilicon. Alternately, Si.sub.3 N.sub.4 may be used as an etch stop layer located on the SiO.sub.2 interlayer dielectric layer to utilize a high etch selectivity between Si.sub.3 N.sub.4 and SiO.sub.2. However, in this case, there arises another problem that the leakage current through a transistor junction increases because of a high stress of Si.sub.3 N.sub.4.
There arises a further problem that Si.sub.3 N.sub.4 is unable to be used as a hard mask for a through hole because of a comparatively high deposition temperature of Si.sub.3 N.sub.4.